1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a circuit for implementing a special mode in a packet-based semiconductor memory device. The present invention is used for a Rambus dynamic random access memory (referred to as a “DRAM” hereinafter) or a packet-based semiconductor memory device.
2. Description of the Prior Art
As generally known in the art, a dynamic random access memory (referred to as a “DRAM” hereinafter) is an element which transmits or receives a digital signal through a bus according to the request of a central processing unit (CPU). Accordingly, a DRAM which does not have a bus transmission function is not useful. DRAM interfaces have been focused on an optimization of an electric signal transmission of a DRAM, such as data width of the DRAM or driving performance of a data output buffer, up to now. A quick and exact transmission of a signal (bit) to the outside according to the request of a CPU has been pursued. However, regarding DRAMs, a quick and exact transmission of data is more important than the transmission of a signal. A transmission of a data unit (referred to as a “packet” hereinafter) having a predetermined size, being more efficient than that of a signal of a bit unit, is on the rise. Under these circumstances, a packet-based DRAM such as a Rambus DRAM has been developed.
A Rambus protocol is a protocol in a Rambus channel which uses a source synchronous bus configuration synchronizing a travel direction of data with a direction of a clock. The Rambus protocol includes a base Rambus DRAM protocol, a concurrent Rambus DRAM protocol, and a direct Rambus DRAM protocol. The direct Rambus DRAM protocol uses an ROWA packet, a row command (referred to as an “ROWR”) packet, a column command (referred to as a “COLC” hereinafter) packet, a column extended command (referred to as a “COLX” hereinafter) packet, and a COLM packet. Functions and configurations of the ROWA, ROWR, COLC, COLM, and COLX packets are different from one another. FIG. 1 is a diagram showing a configuration of a COLC+COLX packet in a conventional Rambus DRAM. In FIG. 1, the COLC packet of the COLC+COLX packet is indicated by bits located outside a dotted line. The COLX (or COLM) packet of the COLC+COLX packet is indicated by bits located inside the dotted line in FIG. 1. When M=1, the bits located inside the dotted line operate as a COLM packet and are used as a mask bit of writing data. When M=0, the bits located inside the dotted line operate as a COLX packet. When the bits located inside the dotted line operate as a COLX packet, the Rambus DRAM performs an operation such as a precharge, a current calibration, and a power conversion to a standby status.
In FIG. 1, DX0 to DX4 in the COLC+COLX packet are bits indicating whether COLX operation is performed by any device. BX0˜BX4 in the COLC+COLX packet are bits indicating whether the COLX operation is performed in any bank of a device specified by DX0˜DX4. XOP0˜XOP4 are bits indicating whether any operation is performed in the bank of a device specified by DX0˜DX4 and BX0˜BX4. At this time, RsvB is not being used as a reserved bit. Table 1 shows command contents of the conventional COLX packet.
TABLE 1XOP4~CommandMDX4~DX0XOP0Titlecontents1. . .—MSKMB/MA byte mask usedby WR/WRA0/=(DEVID4 . . 0)——No operation0 =(DEVID4 . . 0)00000NOXOPNo operation0 =(DEVID4 . . 0)1xxx0PREXPrecharge banks BX4through BX0 of device0 =(DEVID4 . . 0)x10x0CALCurrent IOL cali-bration of device0 =(DEVID4 . . 0)x11x0CAL/SAMIOL calibration andsampling of device0 =(DEVID4 . . 0)xxx10RLXXChange device intostandby power status0 =(DEVID4 . . 0)xxxx1RSRVReservation,no operation
In order to implement a special mode register in a conventional Rambus DRAM, it is necessary to change the special mode register thereof to a control register mode. Also, a control register is used in a limited part such as current control of an output driver and control of a slew rate. The control register is processed by a metal layer option. In the conventional Rambus DRAM having the above configuration, in order to change the special mode register thereof to a control register mode or to additionally check a special part affecting the quality of memory, when a control register is used, embodiment of operations and adding/changing of circuits become complicated. When the control register is processed by the metal layer option, the cost and the time required for the process both increase.